Memory devices are ubiquitous in numerous fields involving computers and electronics. In some cases, memory has been implemented with storage elements capable of storing electrical charge. In other cases, memory has been implemented with storage elements capable storing magnetic orientation. Solid-state magnetic memory arrays may comprise individual storage elements constructed utilizing semiconductor processing techniques.
The individual magnetic elements of the magnetic memory array may comprise materials with varying magnetic properties separated by an insulating layer. The magnetizations of the separated materials may be oriented in the same direction (termed “parallel”), or their orientation may be opposite directions (termed “anti-parallel”). The electrical resistance of the magnetic elements may vary depending on the parallel or anti-parallel orientation of the magnetizations. In this manner, digital information may be stored and retrieved by associating digital values (e.g., 1s and 0s) to the electrical resistance associated with the parallel and anti-parallel states.
The orientation (i.e., parallel or anti-parallel), and consequently the digital value, of a memory element may be configured by inducing a magnetic field in the memory element. Conductors that may be proximate to the memory element may conduct current, and this current may consequently induce a magnetic field in the proximate memory element. The induced magnetic field may then change the orientation of the memory element.
Because memory is often employed in consumer electronics, memory that is high speed, low cost, and low power is desirable. The power consumption, speed, and cost of the memory chip are directly related to the total chip area (i.e., the area of the array of memory elements and accompanying circuitry), and larger chips may be more costly to manufacture. As a result, low cost memory may be built by densely packing memory elements within a memory array. However, the conductors used in configuring the memory elements may undesirably limit the density of the memory elements and add to the size of the chip.
Therefore, it may be difficult to design memory that is fast, cheap, and that consumes low power because the techniques for increasing speed and decreasing power often lead to cost increases and vice versa.